The present disclosure relates to substrate dicing, and particularly, to a method of dicing a substrate for reduction of stress on diced chips, and structures formed by the same.
Dicing is a process in which a chip-containing substrate wafer is cut into individual die. The chip-containing substrate typically includes a vertical stack of a semiconductor structures including semiconductor devices and a metal interconnect structure-containing layer including dielectric material layers and metal interconnect structures embedded therein. Each die typically includes a semiconductor chip, and can be subsequently bonded with another substrate in a bonding process such as flip chip assembly. Typically, a diamond blade dicing process has been used in the industry for singulation of dies from the chip-containing substrate.
Recently, low dielectric constant (low-k) dielectric materials having a dielectric constant less than 3.9 (the dielectric constant of silicon oxide) and porous ultra low-k dielectric materials having a dielectric constant less than 2.8 have been employed as the dielectric material embedding the metal interconnect structures in chip-containing substrates. Because such low-k and ultra low-k dielectric materials are prone to structural damage during saw dicing, formation of grooves in the dielectric material layer embedding metal interconnect structures has been recently adopted. Specifically, a laser grooving process can be performed first on the active side of the chip-containing substrate, i.e., the side at which the dielectric material layer embedding metal interconnect structures are located. Low-k and/or ultra low-k dielectric material layers and metallic structures in the dicing channels are ablated by a laser beam. The metallic structures in the dicing channels typically include test structures and alignment structures, and are referred to as kerf structures. Full singulation of the dies is accomplished by cutting through the remaining portion of the chip-containing substrate, i.e., the semiconductor substrate, in the dicing streets with a diamond saw process.
The low-k and/or ultra low-k dielectric material layers in the metal interconnect layer have a lower mechanical strength than silicon oxide or silicon nitride employed in prior generation semiconductor chips. Thus, diced semiconductor chips including low-k and/or ultra low-k dielectric material layers are more prone to structural damage such as cracking during subsequent packaging steps, which include, for example, thermal cycling steps employed during bonding of a semiconductor chip to a packaging substrate.